Memory devices are ubiquitous in computing devices to store data and code for a processor to execute operations and accomplish the function of the computing devices. Even as the demand for computing devices grows, there is a trend towards smaller computing devices that operate from lower and lower supply voltages. Current memory technologies have been able to continue to scale with the decreasing feature size and decreasing high voltage levels. However, despite being able to produce memory devices with smaller feature sizes, there is still a threshold voltage (Vt) required to access a memory cell, which does not scale with the change in feature size. Thus, the ratio of transistor threshold voltage to supply voltage (Vsu) continues to increase, resulting in shorter cell charge refresh cycle times (based on traditional leakage models). While it is possible to create devices with different leakage models, the cost of such devices makes such an approach impractical.
Shorter refresh cycle time means that a system has to perform more frequent refreshes to maintain state in volatile memories. Requiring more frequent refresh can actually increase power usage in the system, despite lower supply voltages and smaller feature sizes. Additionally, increasing the frequency of refreshing as memory sizes continue to increase poses the possibility that a memory device will be constantly refreshing something. Access to a portion of a memory device that is being refreshed is restricted. Thus, the increased frequency of refreshing will have a negative impact on memory access performance.
Descriptions of certain details and implementations follow, including a description of the figures, which may depict some or all of the embodiments described below, as well as discussing other potential embodiments or implementations of the inventive concepts presented herein.